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CY62128B MoBL
128K x 8 Static RAM
Features
* Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive: -40C to 125C * 4.5V - 5.5V operation * CMOS for optimum speed/power * Low active power (70 ns, LL version, Commercial, Industrial) -- 82.5 mW (max.) (15 mA) * Low standby power (70 ns, LL version, Commercial, Industrial) -- 110 W (max.) (15 A) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options
Functional Description[1]
The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages.
Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER
I/O 0 I/O 1 SENSE AMPS I/O 2 I/O 3 I/O 4 I/O 5
POWER DOWN
512x 256x 8 ARRAY
CE1 CE2 WE OE
COLUMN DECODER
I/O 6 I/O 7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05300 Rev. *C
*
A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 14, 2005
CY62128B MoBL
Product Portfolio
Power Dissipation VCC Range (V) Product CY62128BLL Industrial Industrial Automotive Min. 4.5 Typ.[2] 5.0 Max. 5.5 Speed (ns) 55 70 70 Operating, ICC (mA) Typ.[2] 7.5 6 6 Max. 20 15 25 Standby, ISB2 (A) Typ.[2] 2.5 2.5 2.5 Max. 15 15 25
Pin Configurations
Top View SOIC
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GN G ND g gnc G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE 2 WE A13 A8 A9 A11 OE A10 CE 1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
A16
A12 A14
A7
A4 A5 A6
VCC
NC
A15 CE2 WE A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Reverse TSOP I Top View (not to scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A11 A2 A9 A1 A8 A13 A0 I/O0 WE I/O1 CE2 A15 I/O2 GND VCC NC I/O3 A16 I/O4 A14 I/O5 A12 I/O6 A7 I/O7 A6 CE1 A5 A10 A4 OE
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
Pin Definitions
Input Input/Output Input/Control Input/Control Input/Control Input/Control Ground Power Supply A0-A16. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. CE1. Chip Enable 1, Active LOW. CE2. Chip Enable 2, Active HIGH. OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins GND. Ground for the device VCC. Power supply for the device
Notes: 2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25C, and tAA = 70 ns.
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CY62128B MoBL
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] .................................-0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive Ambient Temperature (TA)[4] 0C to +70C -40C to +85C -40C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY62128B-55 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Load Current Output Leakage Current Output Short Circuit Current[5] VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs GND VI VCC Automotive GND VI VCC, Output Disabled -1 Automotive -300 7.5 20 6 6 0.1 2 0.1 0.1 2.5 15 2.5 2.5 +1 Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.3 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 2.2 -0.3 -1 -10 -1 -10 Typ.[2] Max. CY62128B-70 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +10 +1 +10 -300 15 25 1 2 15 25 Typ.[2] Max. Unit V V V V A A A A mA mA mA mA mA A A
VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 VIH or CE2 < VIL, VIN VIH or VIN VIL, f = fMAX Industrial, Commercial Automotive Industrial Commercial Automotive
ISB1
ISB2
Automatic CE Power-down Current --CMOS Inputs
Industrial Max. VCC, CE1 VCC - 0.3V, Commercial or CE2 0.3V, Automotive VIN VCC - 0.3V, or VIN 0.3V, f = 0
Thermal Resistance[6]
Parameter Description Test Conditions 32 SOIC 32 TSOP 32 STSOP 32 RTSOP 66.17 30.87 97.44 26.05 105.14 14.09 97.44 26.05 Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test (Junction to Ambient) methods and procedures for Thermal Resistance measuring thermal impedance, per EIA / JESD51. (Junction to Case)
Note: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant On" case temperature. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 6. Tested initially and after any design or process changes that may affect these parameters.
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CY62128B MoBL
Capacitance[6]
Parameter CIN COUT
\
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V
Max. 9 9
Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 990 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 990 GND Rise TIme: 1 V/ns R1 1800 VCC ALL INPUT PULSES 90% 10% 90% 10% Fall TIme: 1 V/ns
THEVENIN EQUIVALENT 639 1.77V OUTPUT
Data Retention Characteristics (Over the Operating Range for "LL" version only)
Parameter VDR ICCDR tCDR tR Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE1 VCC - 0.3V, or CE2 0.3V, VIN VCC - 0.3V or, VIN 0.3V 0 70 Conditions Min. 2.0 1.5 15 Typ. Max. Unit V A ns ns
Data Retention Waveform
VCC
CE1
VCC, min. tCDR
DATA RETENTION MODE VDR > 2 V
VCC, min. tR
or CE2
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CY62128B MoBL
Switching Characteristics[7] Over the Operating Range
62128B-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[8, 9] CE1 LOW to Low Z, CE2 HIGH to Low Z[9] CE1 HIGH to High Z, CE2 LOW to High Z[8, 9] 0 55 55 45 45 0 0 45 25 0 5 20 70 60 60 0 0 50 30 0 5 25 CE1 LOW to Power-up, CE2 HIGH to Power-up CE1 HIGH to Power-down, CE2 LOW to Power-down Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[9] Z[8, 9] 5 20 0 70 0 20 5 25 5 55 20 0 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 62128B-70 Min. Max. Unit
WRITE CYCLE[10]
Switching Waveforms
Read Cycle No.1[12, 13]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID
PREVIOUS DATA VALID
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. No input may exceed VCC + 0.5V. 12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 13. WE is HIGH for read cycle.
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CY62128B MoBL
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Write Cycle No. 1 (CE1 or CE2 Controlled)[15, 16]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA
Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
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CY62128B MoBL
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD
Write Cycle No.3 (WE Controlled, OE LOW)[15, 16]
tWC ADDRESS tSCE CE1 CE2
tSCE tAW tSA tPWE tHA
WE tSD DATAI/O NOTE 17 tHZWE
Note: 17. During this period the I/Os are in the output state and input signals should not be applied.
tHD
DATA VALID tLZWE
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CY62128B MoBL
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High Z High Z Data Out Data In High Z Power-down Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62128BLL-55SI CY62128BLL-55SXI CY62128BLL-55SC CY62128BLL-55SXC CY62128BLL-55ZI CY62128BLL-55ZXI CY62128BLL-55ZAI CY62128BLL-55ZAXI CY62128BLL-55ZRI 70 CY62128BLL-70SI CY62128BLL-70SXI CY62128BLL-70SC CY62128BLL-70SXC CY62128BLL-70SE CY62128BLL-70SXE CY62128BLL-70ZI CY62128BLL-70ZXI CY62128BLL-70ZC CY62128BLL-70ZXC CY62128BLL-70ZE CY62128BLL-70ZXE CY62128BLL-70ZAI CY62128BLL-70ZAXI CY62128BLL-70ZAE CY62128BLL-70ZAXE CY62128BLL-70ZRXE Package Name S34 S34 S34 S34 Z32 Z32 ZA32 ZA32 ZR32 S34 S34 S34 S34 S34 S34 Z32 Z32 Z32 Z32 Z32 Z32 ZA32 ZA32 ZA32 ZA32 ZR32 Package Type 32-Lead 450-Mil SOIC 32-Lead 450-Mil SOIC (Pb-free) 32-Lead 450-Mil SOIC 32-Lead 450-Mil SOIC (Pb-free) 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead STSOP Type I 32-Lead STSOP Type I (Pb-free) 32-Lead Reverse TSOP Type I 32-Lead 450-Mil SOIC I 32-Lead 450-Mil SOIC I (Pb-free) 32-Lead 450-Mil SOIC I 32-Lead 450-Mil SOIC I (Pb-free) 32-Lead 450-Mil SOIC I 32-Lead 450-Mil SOIC I (Pb-free) 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead TSOP Type I 32-Lead TSOP Type I (Pb-free) 32-Lead STSOP Type I 32-Lead STSOP Type I (Pb-free) 32-Lead STSOP Type I 32-Lead STSOP Type I (Pb-free) 32-Lead Reverse TSOP Type I (Pb-free) Operating Range Industrial Industrial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Automotive Automotive Industrial Industrial Commercial Commercial Automotive Automotive Industrial Industrial Automotive Automotive Automotive
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CY62128B MoBL
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
16 1
0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600]
0.101[2.565] 0.111[2.819]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508]
0.023[0.584] 0.039[0.990]
SEATING PLANE
51-85081-*B
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
51-85056-*D
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CY62128B MoBL
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32
51-85094-*D
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-*C
MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05300 Rev. *C Page 10 of 11
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62128B MoBL
Document History Page
Document Title: CY62128B MoBL 128K x 8 Static RAM Document Number: 38-05300 REV. ** *A ECN NO. 116566 126601 Issue Date 06/20/02 06/09/03 Orig. of Change DSG JUI Description of Change Changed from Spec number: 38-00524 to 38-05300 Changed CE to CE1 and added CE2 0.3V in Data Retention Characteristics table Removed these part numbers from Ordering Information table: CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC, CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC Added Thermal Resistance table Added Automotive product information Added Pb-free package information
*B *C
239134 321335
See ECN See ECN
AJU AJU
Document #: 38-05300 Rev. *C
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